Bulletin of Electrical Engineering and Informatics
Vol 7, No 2: June 2018

An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM

Rani, Archana ( Manav Rachna International University ) , Grover, Naresh ( Manav Rachna International University )

Article Info

Publish Date
01 Jun 2018


This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route & Placed design.

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Original Source : http://journal.portalgaruda.org/index.php/EEI/article/view/818
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Journal Info






Bulletin of Electrical Engineering and Informatics ISSN: 2302-9285 is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication, computer engineering, computer science, information technology and informatics from the global ...