Pratiwi, Ganjar Febriyani
Universitas Muhammadiyah Semarang

Published : 2 Documents
Articles

Found 2 Documents
Search

PERANCANGAN DISKRIT D FLIP-FLOP MENGGUNAKAN TEKNOLOGI CMOS 0.35 µm Widyastuti, Widyastuti; Afandi, Hamzah; Pratiwi, Ganjar Febriyani
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Original Source | Check in Google Scholar

Abstract

Accumulator dump is one of the tools used to convert serial data into parallel data on RFID communications. Accumulator dump on RFID communication consists of a series of counters and registers, where one of the supporting circuits in the counter and register is D flip-flop. D flip-flops are one type of flip-flop that is built using RS flip-flops. Discrete circuit design Master-slave flip-flops  are  built  using  NAND  logic  gates  built  using  0.35  µ m  CMOS technology. The results of the D flip-flop circuit design are simulated using LT- SPICE software to see the speed of response and power dissipation in the circuit. Keywords: RFID, CMOS 0.35 µ m, D flip-flop, Dump Accumulator, NAND logic
HALF ADDER UNTUK COUNTER PADA METODE DUMP ACCUMULATOR RFID DENGAN TEKNOLOGI 0.35µm Pratiwi, Ganjar Febriyani; Afandi, Hamzah; ‘Ainingsih, Dyah Nur
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Original Source | Check in Google Scholar

Abstract

RFID tags are divided into active RFID tags and passive RFID tags. In this case  using  a  passive  RFID  tag  that  is  supported  by  using  a  13.56  MHz frequency radio signal. RFID technology is used here to monitor nutrients in the nursery process in the planting medium. The method used in sending data via the 13.56 MHz radio frequency is the Accumulator Dump method. Accumulator dump is a method to change the output of Delta Sigma ADC in the form of serial data into parallel data. The accumulator dump is built from a series  of  registers  and  counters.  For  the  counter  circuit  itself  uses  a combination of NAND gate circuits, Flip-Flop D circuits and Half Adder (HA) circuits. For the half adder circuit itself, it consists of an EX-OR gate and an AND gate. By using 0.35u technology, this half adder circuit is designed on LT- Spice tools which require an input voltage of 3.3 Volts with 11 PMOS and 11 NMOS, with a value of W = 1u and L = 0.35u to produce the desired output. The frequency of the half adder circuit is 50Hz with a maximum power consumption of 0.00363Watt. Keywords: Tag RFID Pasif, Dump Accumulator, Counter, Half Adder