Trio Adiono
Microelectronic Center, Institut Teknologi Bandung (ITB)

Published : 19 Documents
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Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE Adiono, Trio; Ramdani, Ahmad Zaky; Putra, Rachmad Vidya Wicaksana
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v8i1.pp198-209

Abstract

Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
A Custom Firmware and Lightweight Battery System Design for Portable RFID Reader Kasan, Hans; Adiono, Trio; Harimurti, Suksmandhira; Hariadi, Farkhad Ihsan
JURNAL INFOTEL Vol 10 No 2 (2018): May 2018
Publisher : LPPM INSTITUT TEKNOLOGI TELKOM PURWOKERTO

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (648.363 KB) | DOI: 10.20895/infotel.v10i2.366

Abstract

Small to large-scale companies mostly have warehouses to store their inventories, and to manage them a warehouse management system is required. A low cost, yet powerful solution is using a portable RFID reader. In RFID portable reader system, there are three components which are the most essential, i.e. host and its firmware, RF module, and battery.. In this paper, we propose a custom firmware design, which is compatible with different RFID reader chips or development boards. The custom firmware is designed to work by triggering the execution of Electronic Product Code (EPC) Generation 2 protocol standard command on the reader chip. Hence, the firmware can fully utilize the reader chip’s command. Furthermore, a lightweight battery system is also designed. Targeting for a high mobility use, a very lightweight Li-Pro battery, weighing of only 0.1 kg, is used for the battery system. It is also able to work at long operating hour up to 4 hours
Rapid Prototyping Methodology of Lightweight Electronic Drivers for Smart Home Appliances Adiono, Trio; Putra, Rachmad Vidya Wicaksana; Fathany, Maulana Yusuf; Lawu, Braham Lawas; Afifah, Khilda; Santriaji, Muhammad Husni; Fuada, Syifaul
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 5: October 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v6i5.pp2114-2124

Abstract

Many researches have been conducted in smart home topic. Mostly, they discussed on the specific aspect of application. On the other side, many applications still can be explored and attached into the system. Several main challenges in designing the application devices are system complexity, reliability, user friendliness, portability, and low power consumption. Thus, design of electronic driver is one of the key elements for overcoming these challenges. Moreover, the drivers have to comply the rules of smart home system, data protocol, and application purpose. Hence, we propose a rapid prototyping methodology on designing lightweight electronic drivers for smart home appliances. This methodology consists of three main aspects, namely smart home system understanding, circuitry concept, and programming concept. By using this method, functional and lightweight drivers can be achieved quickly without major changes and modifications in home electrical system. They can be remotely controlled and monitored anytime and from anywhere. For prototyping, we design several drivers to represent common electronic and mechanical based applications. Experimental results prove that the proposed design methodology can achieve the research target.
An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification Adiono, Trio; Kerkhoff, Hans G.; Kunieda, Hiroaki
Journal of ICT Research and Applications Vol 3, No 1 (2009)
Publisher : ITB Journal Publisher, LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (472.704 KB) | DOI: 10.5614/itbj.ict.2009.3.1.4

Abstract

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.
Nonlinear Dynamic Modeling of a Fixed-Wing Unmanned Aerial Vehicle: a Case Study of Wulung Triputra, Fadjar Rahino; Trilaksono, Bambang Riyanto; Adiono, Trio; Sasongko, Rianto Adhy; Dahsyat, Mohamad
Journal of Mechatronics, Electrical Power, and Vehicular Technology Vol 6, No 1 (2015)
Publisher : Research Centre for Electrical Power and Mechatronics, Indonesian Istitutes of Sciences

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.14203/j.mev.2015.v6.19-30

Abstract

Developing a nonlinear adaptive control system for a fixed-wing unmanned aerial vehicle (UAV) requires a mathematical representation of the system dynamics analytically as a set of differential equations in the form of a strict-feedback systems. This paper presents a method for modeling a nonlinear flight dynamics of the fixed-wing UAV of BPPT Wulung in any conditions of the flight altitude and airspeed for the first step into designing a nonlinear adaptive controller. The model was formed into 10-DOF differential equations in the form of strict-feedback systems which separates the terms of elevator, aileron, rudder and throttle from the model. The model simulation results show the behavior of the flight dynamics of the Wulung UAV and also prove the compliance with the actual flight test results.
Desain Awal Analog Front-End Optical Transceiver untuk Aplikasi Visible Light Communication Adiono, Trio; Fuada, Syifaul; Putra, Angga Pratama; Aska, Yulian
Jurnal Nasional Teknik Elektro dan Teknologi Informasi (JNTETI) Vol 5, No 4 (2016)
Publisher : Jurusan Teknik Elektro dan Teknologi Informasi, Fakultas Teknik, Universitas Gadjah Mada

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1302.057 KB) | DOI: 10.22146/jnteti.v5i4.280

Abstract

Analog Front-End (AFE) is a part of physical layer (PHY) at Visible Light Communications (VLC) system which has important things to transmit and receive the data. This research is a preliminary study in designing AFE transceiver which consists of LED driver and Trans-impedance Amplifier (TIA).The results are used as advanced reference design of AFE system and also to determine the modulations range (analog as well as digital). The design verification is based on data transmission which generated by signal generator. Square wave signal is used as digital modulation representative, and sinusoid signal as analog modulation representatitive. The range of VLC channels is about 50 cm with 0o angle. The result shows that digital modulation bandwidth is about 1 KHz to 10 KHz frequency, and analog modulation bandwidth is from 200 KHz to 600 KHz. We also find a significant impact by adding 1 pF capacitor to reduce noise gain. Furthermore, color filter testing is performed to investigate the design performance.
VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm Putra, Rachmad Vidya Wicaksana; Adiono, Trio
Journal of ICT Research and Applications Vol 10, No 1 (2016)
Publisher : ITB Journal Publisher, LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (981.363 KB) | DOI: 10.5614/itbj.ict.res.appl.2016.10.1.5

Abstract

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
Noise Analysis in VLC Optical Link based Discrette OP-AMP Trans-impedance Amplifier (TIA) Fuada, Syifaul; Adiono, Trio; Putra, Angga Pratama; Aska, Yulian
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 15, No 3: September 2017
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (723.442 KB) | DOI: 10.12928/telkomnika.v15i3.5737

Abstract

To design Visible Light Communication (VLC) system, there are several requirements that needs to be met. One of the requirements is an active component selection (e.g. Op Amp). As an ideal communication system, VLC system has to be able to provides wide bandwidth access with minimum noise. The Transimpedance amplifiers (TIAs) is one of main components in optical system which is placed in the first stage of receiver system. It is used to convert the current output from photodiode to voltage. We have designed a 1 MHz fGBW TIA with low noise (in μVrms range). This paper aims to explain the design and implementation of TIA circuit with photovoltaic topology which cover empirical calculations and simulation of TIA’s bandwidth and its noise sources, i.e. resistor feedback noise, current noise, voltage noise and total noise based on RSS. The OP-AMP is chosen from Texas Instruments product, OPA 380, and photodiode is chosen from OSRAM, SFH213, then simulated by TINA-TI SPICE® software. The noise in TIA circuit is analyzed clearly. The developed kit is ready to be implemented in VLC system.
Desain Sistem Rumah Cerdas berbasis Topologi Mesh dan Protokol Wireless Sensor Network yang Efisien Adiono, Trio; Putra, Rachmad Vidya Wicaksana; Fathany, Maulana Yusuf; Adijarto, Waskita
INKOM Journal Vol 9, No 2 (2015)
Publisher : Pusat Penelitian Informatika - LIPI

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (779.868 KB) | DOI: 10.14203/j.inkom.429

Abstract

Dalam publikasi ini, kami mengusulkan sistem rumah cerdas berdasarkan dua pendekatan. Pendekatan pertama adalah arsitektur bertopologi mesh dan yang kedua adalah protokol Wireless Sensor Network (WSN) yang efisien. Sistem ini memiliki dua lingkungan kerja, indoor dan outdoor. Lingkungan indoor menggunakan sistem WSN, sedangkan lingkungan luar menggunakan sistem internet-cloud. Skema ini dikenal sebagai Internet-of-Things (IoT). Lingkungan indoor dan outdoor terhubung satu sama lain dengan menggunakan suatu jembatan penghubung. Sistem WSN dibentuk dari komponen-komponen WSN yang menggunakan topologi mesh. Setiap komponen dari WSN dirancang untuk mengimplementasikan protokol data efisien yang diusulkan. Untuk lingkungan outdoor, sistem internet-cloud yang ada adalah infrastruktur utama. Dengan demikian, sistem rumah cerdas ini dapat dipantau dan dikendalikan dari ponsel cerdas, kapan saja dan di mana saja, selama akses mobile data tersedia. Untuk evaluasi sistem, beberapa tes telahdilakukan untuk mendapatkan profil sistem.
Design of AXI4-Stream based Modulator IP Core for Visible Light Communication System-on-Chip Setiawan, Erwin; Adiono, Trio
JURNAL INFOTEL Vol 10 No 2 (2018): May 2018
Publisher : LPPM INSTITUT TEKNOLOGI TELKOM PURWOKERTO

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (751.876 KB) | DOI: 10.20895/infotel.v10i2.367

Abstract

In this paper, the design of AXI4-Stream based modulator IP core for Visible Light Communication is reported. The modulator IP core conforms to the AXI4-Stream protocol standard, which is widely used in System-on-Chip (SoC) design. There are three modulation types in this IP core namely, Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), and Quadrature Amplitude Modulation-16 (QAM-16). These modulation types are commonly used in DCO-OFDM system. The modulation types can be selected programmatically from software that runs in main processor by accessing the control register. The output of the modulator is designed for DCO-OFDM modulation using 64-point IFFT. According to the simulation results, this modulator IP core can achieve a throughput of 95.36 Mb/s, 184.77 Mb/s, and 347.81 Mb/s for BPSK, QPSK, and QAM-16, respectively. This modulator IP core is reusable in DCO-OFDM system, so it increases productivity in DCO-OFDM system design.